Power & Signal Integrity Analysis

Signal Integrity Analysis

For high speed system, signal integrity has come to be an outstanding issue. Signal integrity analysis for high speed IO interfaces is critical for the products to function as they are designed to. We provide:

  • High-speed channel analysis: chip to chip signaling analysis
  • Accurate frequency domain model for components
  • Worst case analysis taking into account manufacture tolerance
  • System simulation with both transistor buffers and IBIS model
  • Recommendation of system topology
  • Recommendation of package type, connectors
  • Layout design guideline
  • Recommendation of equalization strategy for IO designs

Power Integrity Analysis

With transistors switching faster, electronic devices become sensitive to power supply noise. It is not rare for incompetent power design to cause system failure. One of the trouble-makers is Simultaneous Switching Noise (SSN), which increases jitter, degrades other timing indicators and triggers logic errors in worse cases. For the device to meet design target, SSN needs to be restrained within allowable amount by choosing the right stack-up, implementing proper power/ground plane layout and decoupling techniques.

Our experience in power delivery network design, modeling, analysis and optimization extends to IC, package, and PCB designs in various applications – computing, communications, automobile, medical care, aviation, etc. We provide:

  • PCB stack-up design
  • Power/ground plane layout scheme
  • Power distribution scheme
  • Power delivery network model extraction
  • Simultaneous switching noise analysis and solution
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